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-- Company: 
-- Engineer: 
-- 
-- Create Date:    12:16:29 03/09/2012 
-- Design Name: 
-- Module Name:    totaal_uart_rx - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity totaal_uart_rx is
	port(
					 serial_in : in std_logic;
					  data_out : out std_logic_vector(7 downto 0);
				  read_buffer : in std_logic;
				 reset_buffer : in std_logic;
				 en_16_x_baud : in std_logic;
		buffer_data_present : out std_logic;
				  buffer_full : out std_logic;
			buffer_half_full : out std_logic;
							 clk : in std_logic);
	
end totaal_uart_rx;

architecture Behavioral of totaal_uart_rx is

component uart_rx is
    Port (            serial_in : in std_logic;
                       data_out : out std_logic_vector(7 downto 0);
                    read_buffer : in std_logic;
                   reset_buffer : in std_logic;
                   en_16_x_baud : in std_logic;
            buffer_data_present : out std_logic;
                    buffer_full : out std_logic;
               buffer_half_full : out std_logic;
                            clk : in std_logic);
    end component;
	 
component uartklok is
    Port ( clk : in  STD_LOGIC;
           uart_klok : out  STD_LOGIC);
end component;

signal clock_gedeeld : std_logic;
	
begin

UART : uart_rx PORT MAP(
		serial_in => serial_in,
		data_out => data_out,
		read_buffer => read_buffer,
		reset_buffer => reset_buffer,
		en_16_x_baud => clock_gedeeld,
		buffer_data_present => buffer_data_present,
		buffer_full => buffer_full,
		buffer_half_full => buffer_half_full,
		clk => clk
	);

	Inst_uartklok: uartklok PORT MAP(
		clk => clk,
		uart_klok => clock_gedeeld
	);

end Behavioral;




library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

package UART_RX_Pack is

component totaal_uart_rx is
	port(
					 serial_in : in std_logic;
					  data_out : out std_logic_vector(7 downto 0);
				  read_buffer : in std_logic;
				 reset_buffer : in std_logic;
				 en_16_x_baud : in std_logic;
		buffer_data_present : out std_logic;
				  buffer_full : out std_logic;
			buffer_half_full : out std_logic;
							 clk : in std_logic);
	
end component; 

end package;